=> An important feature is that when a project is recompiled after a few changes, it will recompile only those files which are changed, and any other files that are dependent on it.
It can be used to compile whole project in well arranged manner and generate your target according to your make rule(which we will discuss later) by entering single command that is make. => Large projects can contain multiple source files which are dependent in one another or arranged in hierarchical manner for example, in order to compile file A, you have to first compile B in order to compile B, you have to first compile C and so on. In simple words, makefile will compile your source code in simple & fast way.
Makefile is a script written in a certain prescribed syntax which helps to build the target output (normally, one or more executables) from source files by compilation and linking.
If you tell your instructor/teacher/prof that an empty makefile is all you need since you know the built-in rules do the right thing, you'll get some extra credit and maybe your instructor has learnt something new :-) If you are asked for a reference, you could quote the relevant parts of the make manual, or, do it like a pro, quote from the POSIX Standard for the make utility, section Default Rules.īefore going for makefile you have to know what's it and why we need it If you want to use gcc instead of cc, you can run $ rm Hello All you need to do is place your C source in a file named after the executable name ( Hello) and with a. Now for your task, really there is no need for a Makefile, since make has built-in rules that know how to compile a simple program. A makefile typically looks like this: target: dependency A makefile is a recipe for the make utility how to create some file (called a target) from some other files (called dependencies) using a set of commands run by the shell.
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